The YGREC8's Manual : the SH opcode

Created lun. 30 oct. 2023 18:36:10 CET by whygee@f-cpu.org

PRELIMINARY / WORK IN PROGRESS

Encoding

Description

SH is one of the 4 optional opcodes using the dedicated "shuffler unit" that performs shifts and rotations. See also SA, RO and RC for the other variations.

SH gets a byte from the SND register, logic-shifts it (like an unsigned division, depending on the value of the SRI operand) and writes it back to SND.

The shift amount from SRI is either a Imm4 or a register, the value is truncated to 4 bits and gives a 1s-complement signed integer. The sign (bit 3) determines the direction of the shift:

• 0001 to 0111 shift left (multiply by power of two)
• 1001 to 1111 shift right (divide by a power of two)
• 0000 and 1000 do nothing

Effects

This instruction affects the Sign and Zero flags, but not the Carry flag.

Forms

This is an optional operation in the "extended opcode" range, which supports only 2 types of operand for SRI, without condition:

• Imm4: a sign-extended immediate value encodes a fixed number from -8 to +7.
• SRI: one of the 8 registers.

Examples

SH 3 R1  ; R1 = R1 << 3

SH -3 R1 ; R1 = R1 >> 3

SH R2 R1 ; R1 shifted depending on the 4 LSB of R2

; TODO : more numerical	examples