Created lun. 30 oct. 2023 19:36:09 CET by whygee@f-cpu.org PRELIMINARY / WORK IN PROGRESS
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | SRI | SND | ||||
| 1 | Imm4 | ||||||||||||||
RC is one of the 4 optional opcodes using the dedicated "shuffler unit" that performs shifts and rotations. See also SA, SH and RO for the other variations.
RC gets a byte from the SND register, rotates it (depending on the value of the SRI operand) through the Carry Flag and writes the result back to SND. The SND and Carry flag are processed together like a 9-bit register.
The rotation amount from SRI is either a Imm4 or a register, the value is truncated to the 3 lower bits (since a 4-bit signed integer would duplicate values).
Bit 6 of the instruction is not decoded or used and should be kept cleared for forward compatibility.
This instruction affects the Carry, Sign and Zero flags.
The carry flag will go to the (N-1)th bit of the destination register, and is overwritten byt the (8-N)th bit of the source register.
This is an optional operation in the "extended opcode" range, which supports only 2 types of operand for SRI, without condition:
RC 3 R1 ; R1 = R1 rotated left by 3 bits
RC -3 R1 ; MUST_FAIL: legal(?) but pointless,
; use RO 5 R1 instead (8-3=5)
; (issue a warning ?)
RC R2 R1 ; R1 rotated depending on the 3 LSB of R2
; TODO : more numerical examples and diagrams.