The YGREC8's Manual : the RO opcode

Created lun. 30 oct. 2023 19:36:09 CET by whygee@f-cpu.org

PRELIMINARY / WORK IN PROGRESS

Encoding

Description

RO is one of the 4 optional opcodes using the dedicated "shuffler unit" that performs shifts and rotations. See also SA, SH and RC for the other variations.

RO gets a byte from the SND register, rotates it (depending on the value of the SRI operand) and writes the result back to SND.

The rotation amount from SRI is either a Imm4 or a register, the value is truncated to the 3 lower bits (since a 4-bit signed integer would duplicate values).

Bit 6 of the instruction is not decoded or used and should be kept cleared for forward compatibility.

Effects

This instruction affects the Sign and Zero flags, but not the Carry flag.

Forms

This is an optional operation in the "extended opcode" range, which supports only 2 types of operand for SRI, without condition:

• Imm4: a sign-extended immediate value encodes a fixed number from -8 to +7. Only the range 0 to 7 is used by RO.
• SRI: one of the 8 registers.

Examples

RO 3 R1  ; R1 = R1 rotated left by 3 bits

RO -3 R1 ; MUST_FAIL: legal(?) but pointless,
         ; use RO 5 R1 instead (8-3=5)
         ; (issue a warning ?)

RO R2 R1 ; R1 rotated depending on the 3 LSB of R2

; TODO : more numerical	examples