The YGREC8's Manual : the PF opcode

Created dim. 29 oct. 2023 23:40:23 CET by whygee@f-cpu.org

PRELIMINARY / WORK IN PROGRESS

Encoding

Description

This opcode is a prefix for the following instruction and modifies its default behaviour.

• The CND3 field selects the value of the Carry Input flag, which defaults to 0 for ADD and 1 for SUB. This allows any condition, internal or external, to be used and reinjected in the datapath.
• The SND field is latched and used as the destination address for the following instruction (if it ever commits a result to the register set).
• Other fields (such as SRI and I/R) are still unused and should remain cleared. They might eventually prevent writeback to the registers (to emulate the CMPx opcodes), modify signedness or operand sizes or types, add immediate bits to operands... It's still unclear. So keep them cleared.

Effects

PF does not affect the Carry, Sign or Zero flags (only the default Carry In value, which is different from the Carry flag).

Forms

This is a core operation that supports only one reduced form of SRI (where the field is not used). It cannot be inhibited but has access to all the 16 conditions.

When the condition is omitted, it is also defaulted to "ALWS" and the Carry In is set to 1.

Examples

PF R1  ; the next instruction will write to R1, default ALWS => Carry In = 1

PF D1 IFN2 ; next instruction writes to D1, Carry In = bit 2.