The YGREC8's Manual : the SUB opcode

Created lun. 30 oct. 2023 02:07:18 CET by whygee@f-cpu.org
Version mar. 31 oct. 2023 17:50:26 CET


PRELIMINARY / WORK IN PROGRESS

Encoding

Description

SUB is practically identical to ADD, but with the SND and default Carry In inverted.

This opcode does a 2s-complement addition of the two operands SRI and the negated SND. Subtraction is achieved by setting the Carry In flag to 1, unless instructed otherwise by PF.

For multi-byte subtractions, the prefix is also required to preload the Carry input, which is otherwise set by default..

Beware of the order of the operands!

Effects

If the condition is valid (or SRI is Imm8), this instruction writes to the register given by the SND field and affects the Carry, Sign and Zero flags.

Forms

This is a core operation that supports 3 types of operand for SRI:

• Imm8: an immediate field of 8 bits is taken directly from the instruction.
• Imm4: a sign-extended immediate value encodes a fixed number from -8 to +7. Can be inhibited by one of 8 conditions.
• SRI: one of the 8 registers. Can be inhibited by one of 16 conditions (the above plus the 4 external condition bits).

However, the Immediate forms are less useful than with ADD.

Examples

SUB R1 R2 ; R2 = R1 - R2

PF R1  ; reverse the destination register:
SUB R1 R2 ; R1 = R1 - R2

SUB 123 R3 ; R3 = 123 - R3

SUB 0 R1 IFNZ ; Negate R1 if last result is not zero

; TODO : multi-byte subtraction