The YGREC8's Manual : the ADD opcode

Created sam. 14 oct. 2023 04:18:11 CEST by whygee@f-cpu.org
version jeu. 19 oct. 2023 04:47:17 CEST : removed the "carry on Imm4" trick
version dim. 29 oct. 2023 23:40:23 CET

PRELIMINARY / WORK IN PROGRESS

Encoding

Description

This opcode does a 2s-complement addition of the two operands SRI and SND.

If the destination register (SND unless instructed otherwise by PF) is PC, this performs a relative jump (with a one-cycle penalty because the new address is available at the end of the cycle and the new instruction needs a cycle to fetch).

Also often used to advance a pointer in memory, for example incrementing or decrementing the stack pointer.

For multi-byte additions, a prefix is required to preload the default-cleared Carry input (see the last example below). Note : the carry can be loaded from any condition and even inverted, which could be useful for deserialisation of bit streams, or whatever trick you fancy.

Effects

If the condition is valid (or SRI is Imm8), this instruction writes to the register given by the SND field and affects the Carry, Sign and Zero flags.

• If the sum exceeds 255, the results wraps around and the C flag is set (otherwise it is cleared)
• If the result's bit 7 (MSB) is 1 then the S flag is set (otherwise it is cleared)
• If the result (truncated to 8bits) is 0 then the Z flag is set (otherwise it is cleared)

Forms

This is a core operation that supports 3 types of operand for SRI:

• Imm8: an immediate field of 8 bits is taken directly from the instruction.
• Imm4: a sign-extended immediate value encodes a fixed number from -8 to +7. Can be inhibited by one of 8 conditions.
• SRI: one of the 8 registers. Can be inhibited by one of 16 conditions (the above plus the 4 external condition bits).

Examples

ADD R1 R2 ; R2 = R1 + R2

ADD 123 R3 ; R3 = R3 + 123

PF R3
ADD R1 R2 ; R3 = R1 + R2


; increment:
ADD 1 R1  ; R1 = R1 + 1

; decrement:
ADD -1 R1 ; R1 = R1 - 1

; add 5 if Zero flag is set
ADD 5 R1 IFZ ; R1 = R1 + 5

; add R2 to R1 if B2 is not set
ADD R2 R1 IF2

; If R1==42 then do something:
CMPU 42 R1   ; update the Z flag
ADD 7 PC IFNZ  ; skip up to 7 instructions if Z is cleared
  NOP ; 1
  NOP ; 2
  NOP ; 3  conditional block
  NOP ; 4
  NOP ; 5
  NOP ; 6
; end of conditional block: 7th instruction here


; Add 16 bits (R1,R2)+=(D1,D2)
ADD D1, R1 ; might generate a carry
PF R2 IFC  ; preload the Carry flag into the ALU's carry input
ADD D2, R2 ; R2=R2+D2+C


; emulate a shift-left-through-carry
; (serial input in B0, parallel output in R1)
PF R1 IF0
ADD R1 R1 ; x+x=2x, shift left, fill LSB with b0