The YGREC8's Manual : the CMPU opcode

Created lun. 30 oct. 2023 02:07:18 CET by whygee@f-cpu.org
version lun. 13 nov. 2023 23:59:56 CET


PRELIMINARY / WORK IN PROGRESS

Encoding

Description

CMPU is the unsigned complementary opcode to the signed CMPS and is directly derived from SUB, except the SND register is not written back.

CMPU subtracts the SND operand from the SRI operand and updates the flags (if not inhibited). This is useful for testing conditions before a jump to skip other instructions or to loop back and repeat code.

Multi-byte comparisons are possible with the help of the PF prefix.

Beware of the order of the operands!

Effects

If the condition is valid (or SRI is Imm8), this instruction affects the Carry, Sign and Zero flags.

Forms

This is a core operation that supports 3 types of operand for SRI:

• Imm8: an immediate field of 8 bits is taken directly from the instruction.
• Imm4: a sign-extended immediate value encodes a fixed number from -8 to +7. Can be inhibited by one of 8 conditions.
• SRI: one of the 8 registers. Can be inhibited by one of 16 conditions (the above plus the 4 external condition bits).

Examples

; this code loops 42 times:
set 0 R1

loop:
  add 1 R1
  cmpu 42 R1
  add -2 PC IFNZ

; TODO : multi-byte comparison