Created lun. 30 oct. 2023 02:40:13 CET by whygee@f-cpu.org version lun. 13 nov. 2023 23:59:56 CET PRELIMINARY / WORK IN PROGRESS
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 0 | 1 | 0 | 0 | N | CND3 | SRI | SND | ||||||
| 1 | CND2 | Imm4 | |||||||||||||
| 1 | IMM8 | ||||||||||||||
CMPS is the signed complementary opcode to the unsigned CMPU and is directly derived from SUB, except the SND register is not written back.
CMPS toggles the sign bit (MSB) of both operands before performing the comparison. It then subtracts the SND operand from the SRI operand and updates the flags (if not inhibited). This is useful for testing conditions before a jump to skip other instructions or to loop back and repeat code.
The tiny difference between CMPU and CMPS is CMPS considers that SND and SRI are signed. However the Adder is inherently unsigned. The "trick" is to invert the MSB of the operands to wrap the -128..127 ranges back to 0..255. This only adds one XOR in the SRI datapath but nothing in the SND path, since the subtraction already inverts all the bits. So the CMPS opcode simply inhibits the XOR of the SND's MSB. This opcode really comes with very little overhead!
Multi-byte comparisons are possible with the help of the PF prefix.
Beware of the order of the operands!
If the condition is valid (or SRI is Imm8), this instruction affects the Carry, Sign and Zero flags.
This is a core operation that supports 3 types of operand for SRI:
; this code loops 42 times: set -22 R1 loop: add 1 R1 cmps 21 R1 add -2 PC IFNZ ; TODO : multi-byte comparison