The YGREC8's Manual : the CALL opcode

Created sam. 14 oct. 2023 05:12:45 CEST by whygee@f-cpu.org
version dim. 29 oct. 2023 23:40:23 CET

PRELIMINARY / WORK IN PROGRESS

Encoding

Description

Also known as "Jump And Link" (JAL), this opcode is a version of the SET opcode that performs a swap through the PC: instead of copying the SRI operand into SND,

• The SRI operand is used as the address of the next instruction instead of PC+1,
• SND receives PC+1.

Since it affects the PC, the datapath must be optimised to reduce the latency. There is a direct path between the SRI selectors and the instruction address port, multiplexed with the output of the PC incrementer, so the next instruction is available by the end of the current cycle (when possible). This path avoids the extra cycle of the "write-to-PC" operations (such as PC-relative branches that must go through the ALU).

If the SND register is PC then the opcode becomes OVL and triggers a change of overlay.

If on top of SND=PC, the Imm8 address is FFh, then the core halts (HLT pseudo-opcode).

Effects

CALL does not affect the Carry, Sign or Zero flags.

The OVL form would affect overlay-related registers and/or pause the core while new code is being loaded.

Forms

This is a core operation that supports all 3 types of operand for SRI:

• Imm8: an immediate field of 8 bits is taken directly from the instruction.
• Imm4: a sign-extended immediate value (not very useful, but heh.). Can be inhibited by a one of 8 conditions.
• SRI: one of the 8 registers. Can be inhibited by a one of 16 conditions.

Examples

CALL R1 R2 ; Jump to address in R1, saves return address in R2

CALL 123 R3 ; jump to address 123, saves return address in R3

CALL R3 R1 IFZ ; Call address in R3, save in R1, if previous result is 0

CALL 46, PC ; effectively an OVL instruction, that switches to overlay #46

OVL 46 ; the equivalent of the previous line.

OVL 255 ; Overlay #255 manages program terminations.

HLT ; Equivalent of the previous line.