The YGREC8's Manual : the `SET` opcode

Created sam. 14 oct. 2023 05:01:20 CEST by whygee@f-cpu.org
version dim. 29 oct. 2023 23:40:23 CET

PRELIMINARY / WORK IN PROGRESS

Encoding

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	0	N	CND3			SRI			SND
				0	1	N	CND2		Imm4
				1	IMM8

Description

This opcode copies the SRI operand into SND. This is the favoured method to inject immediate data into registers, for example.

If the destination register (SND unless instructed otherwise by PF) is PC, this performs a jump.

Effects

SET does not affect the Carry, Sign or Zero flags.

Forms

This is a core operation that supports all 3 types of operand for SRI:

Imm8: an immediate field of 8 bits is taken directly from the instruction.
Imm4: a sign-extended immediate value. Can be inhibited by a one of 8 conditions.
SRI: one of the 8 registers. Can be inhibited by a one of 16 conditions.

Examples

SET R1 R2 ; R2 = R1

SET 123 R3 ; R3 = 123

; set to 5 if Zero flag is set
SET 5 R1 IFZ ; R1 = 5 if previous result is 0

; copies the value of R2 into R1 if B0 is set
SET R2 R1 IF0