The YGREC8's Manual : the LDCH opcode

Created lun. 30 oct. 2023 02:57:44 CET by whygee@f-cpu.org

PRELIMINARY / WORK IN PROGRESS

Encoding

Description

LDCH is the complementary opcode to the LDCL opcode.

LDCH fetches data from the program memory space and writes the Most Significant Byte from the instruction to the SND register.

This instruction helps implement constant tables that could be read in-place or stored in an overly before being moved to data memory (for example). So it mostly makes sense when used with the SRI register operand along with the .BH pseudo-instruction.

Effects

This instruction does not affect the Carry, Sign and Zero flags.

Forms

This is an optional operation in the "extended opcode" range, which supports only 2 types of operand for SRI, without condition:

• Imm4: a sign-extended immediate value encodes a fixed number from -8 to +7.
• SRI: one of the 8 registers.

Examples

LDCH -2 R1 ; quite pointless since it
  ; could be directly done with SET

; this code sends 12 constant bytes to an IO register:
set start_string R1

  ldch R1 R2 ; load the constant from program memory
  out 123 R2 ; send the constant to I/O
  add 1 R1
  cmpu end_string R1
  add -4 PC IFNZ

HLT

start_string:
  .BH 12, "hello world!\n"
end_string: