The YGREC8's Manual : the AND opcode

Created dim. 29 oct. 2023 23:40:23 CET by whygee@f-cpu.org

PRELIMINARY / WORK IN PROGRESS

Encoding

Description

This opcode takes the SRI operand and masks its bit with the negated SND operand. The result is written back to the SND register. It is intended for arbitrary selectrion (multiplexing) between two bytes, depending on the value of a mask byte.

If the destination register (SND unless instructed otherwise by PF) is PC, this performs a jump. But it's pretty dumb.

Effects

ANDN affects the Sign and Zero flags but not the Carry.

Forms

This is a core operation that supports all 3 types of operand for SRI (though the immediate forms make very little sense but are available anyway for the sake of orthogonality):

• Imm8: an immediate field of 8 bits is taken directly from the instruction.
• Imm4: a sign-extended immediate value. Can be inhibited by a one of 8 conditions.
• SRI: one of the 8 registers. Can be inhibited by a one of 16 conditions.

Examples

ANDN R1 R2 ; R2 = ~R2 & R1

ANDN 123 R3 ; R3 = ~R3 & 123

ANDN R2 R1 IF0 ; whatever, it's legal.

ANDN 2 R3 IFNS ; it's legal, too.

; here is how to multiplex/select arbitrary bits
; from two operands R1 and R2, and merge them into
; one byte in R3:
SET 01101101b R3 ; some mask (usually not a constant)
AND R3, R1  ; all 1s in R3 will keep R1's bits
ANDN R2, R3 ; R3 is negated then ANDed with R2
OR R1 R3    ; merge the two temporary results
; note: only R1 and R3 are modified