The YGREC8's Manual : the `AND` opcode

Created dim. 29 oct. 2023 23:40:23 CET by whygee@f-cpu.org

PRELIMINARY / WORK IN PROGRESS

Encoding

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	0	N	CND3			SRI			SND
				0	1	N	CND2		Imm4
				1	IMM8

Description

This opcode takes the SRI operand and computes a boolean multiplication (masking) with the SND operand, then writes the result back into SND.

If the destination register (SND unless instructed otherwise by PF) is PC, this performs a jump. But it's pretty dumb.

Effects

AND affects the Sign and Zero flags but not the Carry.

Forms

This is a core operation that supports all 3 types of operand for SRI:

Imm8: an immediate field of 8 bits is taken directly from the instruction.
Imm4: a sign-extended immediate value. Can be inhibited by a one of 8 conditions.
SRI: one of the 8 registers. Can be inhibited by a one of 16 conditions.

Examples

AND R1 R2 ; R2 = R2 & R1

AND 123 R3 ; R3 = R3 & 123

; mask R2's bits into R1 if external bit 1 is set
AND R2 R1 IF0

; keep only bit 1 of R3 if the last result was positive
AND 2 R3 IFNS